32nm 3.1 Billion Transistor 12-wide-issue Itanium® processor for Mission-critical Servers
R. J. Riedlinger, R. Bhatia, L. Biro, B. Bowhill, E. Fetzer, P. Gronowski, T. Grutkowski
Intel, Fort Collins, CO
Intel, Hudson, MA
An Itanium® processor implemented in 32nm CMOS with 9 layers of Cu contains 3.1 billion transistors. The die measures 18.2×29.9mm2. The processor has 8 multi-threaded cores, a ring-based system interface and combined cache on the die is 50MB. High speed links allow for peak processor-toprocessor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s.