．A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor
Microprocessor global clock distribution networks use long buffered wires where reflections can be significant. Using accurate transmission-line models and optimization, these reflection effects can be exploited to improve clock-distribution characteristics. The clock distribution network of the POWER6 microprocessor is designed to run at frequencies exceeding 5GHz using only inverters and transmission lines and is capable of on-the-fly duty-cycle correction.．4GHz+ Low Latency Fixed-Point and Binary Floation-Point Execution Units for the POWER6 Processor
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases.．A 5.6GHz 64KB Dual-Read Data Cache for the POWER6 Processor
A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per POWER6 core is presented. The array utilizes a 0.75μm2 butted-junction split-wordline 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical unclamped bitlines for enhanced cell stability and performance.感想：這個Ultra High Frequency還真的是有夠high啊....
