[IEEE ISSCC 2008]終わりの始まり...

ISSCC2008的Advance program已經公佈好一段時日，大概是我最近太懶惰了，遲遲沒有更新blog。

Intel將在ISSCC 2008發表的兩篇論文，正式披露65nm製程四核心Itanium "Tukwila"的大略規格。

4.6 A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor
4:15 PM
B. Stackhouse
Intel, Fort Collins, CO

An Itanium® processor is implemented in 8M 65nm CMOS and measures 21.5×32.5mm2. The processor has four dual-threaded cores, a system interface and 30MB of cache. Quickpath high-speed links enable peak processor-to-processor bandwidth of 96GB/s and peak memory bandwidth of 34GB/s.

4.7 Circuit Design for Voltage Scaling and SER Immunity on a Quad-CoreItanium® Processor
4:45 PM
D. Krueger(1), E. Francom(1), J. Langsdorf(2)
(1)Intel, Fort Collins, CO
(2)Intel, Hudson, MA

A 700mm2 65nm Itanium® processor triples the logic circuitry of its predecessor. Voltage-frequency scaling to contain power consumption is improved by circuit changes that enable lower voltage operation. Furthermore, per-socket error rate is held constant with the use of SER-hardened latches and register files that reduce SER by 80 to 100× over unprotected structures.

可以確定幾件事情：

一、我錯了，Tukwila的die size竟然是我原先預估的兩倍，邏輯電路高達Montecito/Montvale的三倍，天啊。果然4 channel FB-DIMM Gen2 memory controller與4 full width/2 half width QPI外加directory cache會吃掉不少電路和die area...我也開始好奇Nehalem-EX (Beckton)會變成何等龐然大物。

二、QPI設計之初就保留了整合directory cache coherence protocol的彈性，這我倒是有點後知後覺。30MB扣掉24MB L2剩下的6MB，大概幾乎都是directory cache（和redundancy SRAM），假如L1沒有變大的話。

三、回過頭來，一顆如此巨大的怪物，TDP卻只有170W？我只能說，Intel的製程能力實在太強了。

最後，標題「終わりの始まり」取自ひぐらしのなく頃に解第十六話，算是有感而發。現在還說不太上來我真正的感受。不過，看著也即將在ISSCC 2008同時發表的Silverthorne，也許Intel追求的"Full Dominance"，早已伸手可及，為時不遠矣。