不過這些都不重要了，重要的是我在Yahoo找到的這篇文章，特此備份：
IBM's Power6 Gets First Silicon as Power5+ Looms
By Timothy Prickett Morgan
The word on the street is that IBM Corp last month achieved first silicon on its forthcoming Power6 chip, due in servers perhaps in late 2006 and maybe in early 2007, just as it is getting ready to ship a kicker to the current Power5, appropriately called the Power5+ chip. The rumors have it that Big Blue is getting ready to launch the Power5+ in its pSeries AIX-based server line in September or October, which is consistent with past announcements and customer expectations.
IBM (NYSE: IBM-news) refused to comment on the veracity of these rumors, as is the traditional stance of all IT vendors when it comes to rumors about the timing and technical features of future products--excepting their own statements and roadmaps, of course.
Various high-level sources at IBM were very clear in late 2004, and again in early 2005, that the iSeries line of servers, also based on the "Squadron" server design and the Power5 processors, like the pSeries line of machines, would not be upgraded to Power5+ processors in 2005. While IBM has not said why this is the case, it is not hard to surmise.
The Power5+ chips will be using a new 90 nanometer chip-making process, and the yields will not be particularly high. Every one of them that comes off the line working properly will be precious, and will be delivered to customers who need the absolute best raw performance that IBM can bring to bear in the server market.
IBM has direct competition in the Unix market, and Power5+ is really aimed at these customers. To put it bluntly, in terms of green-screen performance, the iSeries line was overkill for most customers back in the late 1990s with the S-Star and I-Star processor lines, so the Power5+ must be a nuclear holocaust or something (to take a bad analogy and make it worse, with my apologies to Paul McCartney on that parenthetical).
The Power5+ chip will be a shrink of the current Power5 chip, which is based on a 130 nanometer, copper/SOI process used first in the 1.7 GHz Power4+ chip that came out in July 2003 and was subsequently used to create the 1.9 GHz Power4+ in February 2004. With the Power5+ chips, IBM is moving to a 90 nanometer copper/SOI process, a very similar process that is being used by IBM to create the "Cell" PowerPC processor that will be used by Sony and Toshiba in various electronic devices.
While IBM will probably implement some circuitry changes in the Power5+ chip, the rumor is that there will be no significant changes to the cores in the processors. IBM could possibly increase the size of the on-chip L2 cache, which is shared by both cores in the Power4 and Power5 families of chips. For instance, when IBM moved from the Power4 to the Power4+ chip, it increased the size of that shared L2 cache to 1.9 MB from 1.4 MB. IBM could tweak other things here and there, but the Power5+ chip should plug into existing Squadron machines; most server designs are created to handle at least two generations of processors.
It would be interesting if IBM could boost the logical partitioning capabilities of the Squadron platform with the Power5+ chips, perhaps doubling from the current 10 partitions per processor core to 20 partitions--or even higher. With anywhere between 30 and 60% higher performance (comparing a 1.9 GHz Power5 chip to a 2.5 GHz or 3 GHz Power5+ chip), there should be room to do this. Many customers would love to support more than 254 partitions on a big Squadron box, and frankly, it might even make sense for IBM to quadruple this and really go after big server consolidation jobs.
The main benefits of the Power5+ chip should be much lower power consumption and heat dissipation in the same clock speed range, as well as more performance in about the same heat range. The Power5 processors run at 1.5 GHz, 1.65 GHz, and 1.9 GHz (with the two lower speeds available in the iSeries line and the top-end speed only available in pSeries machines where the extra performance is critical). As I have said before, because of the differing performance and heat constraints of the server market, I think IBM will probably offer a wider variety of clock speeds for the Power5+ generation, allowing customers to push up into the 2.5 GHz to 3 GHz range for machines with about the same CPU thermals and maybe even down into the 1.5 GHz range or a little lower for customers who want about the performance as the Power5s, but with half or less of the power consumption and heat dissipation.
If IBM doesn't offer customers options that trade off compute power and heat, it is being silly; this is what its main competitors in server processors--Intel Corp (NASDAQ: INTC - news) and Advanced Micro Devices (NYSE: AMD - news) --are doing. Such a chip, running at as little as 1 GHz, would make a nice entry iSeries processor. IBM, if you have a lot of duds that don't run at 2.5 GHz, make some puppy iSeries boxes out of them--don't throw them in the trash.
Moreover, offering a low-speed, low-heat Power5+ would allow IBM to create a very powerful hybrid AIX/Linux workstation. Hewlett-Packard Co and Sun Microsystems Inc (NASDAQ: SUNW - news) have let their Unix workstation lines languish--HP withdrew support of HP-UX on Itanium workstations last summer, in fact. So there is a chance to go after flops-hungry workstation customers with Power5+ as well. But IBM may not go for this opportunity if Power5+ yields are not high.
Considering the trouble IBM's Microelectronics Division had getting its 90 nanometer processes online--and one of the reasons why it has lost Apple as a chip customer--it is hard to believe that IBM will have the chip volumes to do pSeries servers with Power5+ in 2005, and then maybe add some iSeries servers in 2006 (perhaps when i5/OS V5R4 debuts sometime next year), and then do maybe 10 times the volume of these servers in Unix/Linux workstations using Power5. But, if it could get yields on 90 nanometer for Apple Computer (NASDAQ: AAPL - news) (eventually), maybe it can get yields for a workstation line, too.
Power6: To ECLipz or Not to ECLipz
There is a lot of chatter about what Power6 is and isn't and 18 months has not really cleared up the confusion about what IBM future Power6 processor is and isn't. IBM finished up the design of the chip earlier this year (prior to March, and I am not sure when) and did what is called a "tape out," which means the data that describes the process by which you make the masks to make the chips is finished and sent to the chip factory (also called a fab) so they can start making the chips.
When the first chips that function come off the assembly lines at the factory (in this case, IBM's 90 nanometer, 300mm wafer facility in East Fishkill, New York), this is called "first silicon." According to my sources, the Power6 went into first silicon sometime in July, and IBM has actually put the chips into test systems. Those sources say that IBM has booted the open source Linux operating system on the Power6 chips, but has not yet put the AIX or i5/OS operating systems on them.
The Power chip roadmaps from a few years ago caused some confusion in that they indicated that IBM would be using a 65 nanometer process for these chips, due in 2006 and 2007, and could be ramping clock speeds up as high as 6 GHz. The roadmap characterized the clock speeds on the Power6 chips as "ultra high frequency," and unlike the Power4, Power5, and Power5+ chips on the roadmap, the Power6 item did not show two cores, but simply an area that said "cores," plural. It also said "L2 caches," and said "Advanced System Features" instead of the distributed switch that occupies two sides of every Power4, Power4+, Power5, and Power5+ chip.
This distributed switch is the high-speed interconnection that allows four dual-core Power chips to be lashed together into an eight-way SMP server inside a multichip module (MCM), which is a single piece of electronics that is about as big as the palm of your hand. This MCM also contains the L3 caches. To make a big SMP box, like the 64-way Squadron i5 595 and p5 595 machines, you put eight of these eight-core MCMs on cell boards (which IBM calls books) and you have made a big, bad box.
Contrary to what a lot of people have written based on earlier roadmaps and IBM's own statements, the initial Power6 chips will use the same 90 nanometer process that is used for the Power5+ chip. Further down the road--perhaps in the late spring or late summer of 2007--IBM will roll out its Power6+ chips using a future 65 nanometer processes.
Earlier this year, in clarifying Power6 clock speeds, IBM sources told me that the leap from Power5 to Power6 will involve a big jump in gigahertz--more than the jump from Power4 to Power5. The fastest initial Power4 clocked at 1.3 GHz, and the fastest Power5 clocks at 1.9 GHz, which is a bump of 46%. It seems likely that Power6 chips will probably start out at 3 GHz and then push up to 4 GHz. If it can keep the Power6 in the same thermal envelope of the Power5s, there is no reason not to do this.
I think it highly unlikely that IBM will try to push clock speeds to 6 GHz as the initial Power6 specs suggested a number of years ago. Rather than do this, I think IBM will probably have brought more electronics onto the Power6 core to boost performance. If L3 caches are not shrunk and then integrated on the chip with the Power5+, you can bet IBM will do it with the Power6, and then possibly add an external L4 cache to keep those hungry processors fed.
IBM could, of course, add more processor cores to the Power chip with the Power6. Intel is trying to get its "Tukwila" Itanium chip out the door in 2007. Tukwila is expected to have at least four Itanium cores per chip and, like the Power6+, it will use a 65 nanometer manufacturing process. IBM could take this four-core approach with Power6+ and keep the clock speed relatively low on Power6 core and dial up the number of cores on the chip from two to four. Could is the key word here.
IBM has plenty of time to change its mind with Power6+, even if Power6 is done. Remember, Intel was going to ship Montecito a year ago, but them, after taking a drubbing from IBM with the Power4 chips, decided to make Montecito a dual-core rather than a single-core chip. IBM could redraw its roadmap for Power6+ in the same way, keeping the clock speeds low and doubling the cores. On multi-threaded jobs, a four-core Power6+ chip would have four physical threads and four virtual threads though SMT, and keeping the chip count the same as the Squadron boxes, that would mean a big Power6+ box would have 256 threads. This would help databases a great deal, but its value to big batch jobs would be limited. What seems clear is that we are going to have to figure out how to thread batch jobs on all computer architectures.
Having said all that, given IBM's whole "system on a chip" philosophy, I think Big Blue might put off four cores until Power6+ in 2007, and maybe even Power7 in 2008.
Take a look at the history (and breathe deeply before you read this): The Power4 chip put what were essentially two S-Star PowerPC cores with their own L1 caches, the L1 cache controllers, a shared L2 cache, and a single L2 cache controller onto the chip and put the L3 cache off the die. With Power5, IBM added simultaneous multithreading (SMT), doubled the speed of the distributed switch interconnection on chips so it ran at full clock speed (it was half speed on the Power4s), boosted the size of the L2 cache, went from two-way to four-way set association for the caches, moved the L3 cache controller into the chip, moved the L3 cache into the chip package and, most importantly, hung that L3 cache off the L2 cache with a direct link rather than making it go through the interconnection fabric of the MCM, which it did with the Power4. (This wickedly reduced memory latencies.)
I think Power6 will include an on-die L3 cache for each core (or maybe shared by two cores), hung off of individual L2 caches (one per each core), plus an integrated L4 controller, and L4 cache that is implemented in the MCM packaging like L3 caches are today on the Power5s. As I speculated a few months ago, I think there is also a possibility that IBM ditches this hierarchical cache structure and creates a whole new scheme above the L2 caches in each core that boosts memory bandwidth beyond what is possible with a staged cache architecture.
Here's another interesting idea: Imagine (Paris: FR0004150647 - news) if IBM used its thermal conduction module (TCM) technology from mainframes to put an entire 32-chip, 64-core machine in four blocks of ceramic, thus shortening many of the wires in a server complex and significantly reducing interprocessor and memory latencies to the very limits of physics? IBM could do this TCM packaging with the Power6, or hold off until the Power6+. IBM seems to have removed the distributed switch with the Power6 design and replaced it with "advanced system features." What is more advanced than a mainframe's TCM?
What seems clear is that the Power6 chip has been a major redesign, according to my sources, and much of this redesign is being driven apparently by the necessities of moving to a 65 nanometer chip making process. But it may also be done so IBM can do the full tilt TCM integration like it does in mainframes for its very high-end i5 and p5 boxes, as well as deliver single chip, dual-core Power6 chips for volume markets where a TCM is overkill. I think IBM is also committed to getting low-power, dual-core Power6s into entry and midrange servers, blade servers, and even embedded devices. IBM is concerned about power management, which is why it is merging simultaneous multithreading and multiple cores in the Power5 design. Both of these technologies make better use of transistors, and deliver performance without having to add significantly to clock speed.
IBM has also hinted that the Power6 chips will add a lot more functions for self-management from the microcode underpinning OS/400 and AIX, and now its Virtualization Engine hypervisor, into the Power6 chip itself. It would not be surprising for the large pieces of the virtualization embodied in the Virtualization Engine to somehow be implemented in chip transistors and firmware loaded into the processor. Intel and AMD are embedding X86 instruction set virtualization in their chips using their respective VT and Pacifica technologies. IBM could do something similar, providing electronic assist to Virtualization Engine.
The Power6 chip could, being implemented as a TCM, also consolidate the iSeries, pSeries, and zSeries lines down in some way to support mainframe as well as i5/OS, AIX, Linux workloads on the same processor complexes. This is the fabled "Project ECLipz," which IBM has not confirmed and has weakly denied. Exactly how mainframe workloads might be supported is unclear, but there is certainly a prospect of mixing and matching zSeries and Power6 processors within the same complex or TCM.
Using mainframe simulation software from Transitive is also an option. That is how Apple is going to be supporting Power-based workloads on Intel's chips in its future machines. QuickTransit, Transitive's emulation software, can already support mainframe workloads on Power, Xeon, Itanium, and Opteron processors. IBM might go so far as to license Transitive's QuickTransit, implement much of its features in silicon, and put that inside a Power6 or Power7 TCM to make a hybrid mainframe-Power box.
For ECLipz, IBM could also implement zSeries processor instructions in "millicode," a kind of on-chip microcode that would create a CISC mainframe instruction from a bunch of RISC instructions. The zSeries processors already do this a little, by the way, and so does an Itanium chip do this when it is running HP-UX workloads since the Itanium doesn't support PA-RISC instructions. Even the Pentium chip that is probably on your desktop uses similar technology; that Pentium is not using the 80486 instruction set, but has a RISC-like core that assembles these 486 CISC instructions out of smaller RISC instructions. It just tricks the software into thinking it is running 486 instructions.
Whatever IBM has decided, with the Power6 chip in first silicon, whatever it is going to do in terms of core count and mainframe support can now be found out. It is now just a matter of time.
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