媽的，真的被騙了，Nehalem-EP的確是三層cache

"Nehalem will provide dramatic performance and energy improvements to Intel's current industry-leading microprocessors. Nehalem is scalable with future versions having anywhere from 2 to 8 cores, with Simultaneous Multi-threading, resulting in 4 to 16 thread capability. Nehalem will deliver 4 times the memory bandwidth compared to today's highest-performance Intel Xeon processor-based systems. With up to 8 MB level-3 cache, 731 million transistors, Quickpath interconnects (up to 25.6GB per second), integrated memory controller and optional integrated graphics, Nehalem will eventually scale from notebooks to high-performance servers. Other features discussed include support for DDR3-800, 1066, and 1333 memory, SSE4.2 instructions, 32KB instruction cache, 32KB Data Cache, 256K L2 data and instruction low-latency cache per core and new 2-level TLB (Translation Lookaside Buffer) hierarchy. These technical improvements will result in performance improvements as well as flexibility for a wide range of eventual products based on the Nehalem architecture. Gelsinger also discussed the new Tylersburg platform, which can be configured for both one socket High End Desktop (HEDT) and two socket (HPC and dual processing server) operation."

IDF之父Pat Gelsinger的簡報