"When a store is performed, the processor naturally performs a lookup in the L1 Data Cache. If a store is performed and it results in a Data Cache hit, the processor also performs a lookup in the Trace Cache. It the Trace Cache contains any instructions from the same 1K memory area, this triggers an SMC condition."
"If the processor reads code from the same 2kB-aligned area of memory that the executing program is currently writing to, this triggers an SMC condition."
"One processor may fetch code from a page of memory and another processor may update data items that reside within that same page. When the second processor initiates a store to that page (and assuming the page is designated as WB memory) and the store misses its caches, it initiates a Memory Read and Invalidate transaction on the FSB. This is snooped in the first processor's caches including its Trace Cache. If it results in a hit on the Trace Cache, this triggers an SMC condition."
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