星期三, 11月 12, 2008

clockless的Asynchronous Wave Pipeline

Fault Tolerant Clockless Wave Pipeline Design
Wave pipeline is a pipeline processing technique that can increase the throughput without internal storage spaces and power proposed by Cotton in 1969[4]. Multiple data waves can propagate through the wave pipeline from the PI(Primary Input) to the PO(Primary Output) simultaneously without internal latching. It can achieve the theoretical maximum performance, and draws lots of attentions in the industry nowadays.

Assurance and optimization of yield and reliability is a key to the success of clockless asynchronous wave pipeline technique. Ideally, all path delays from PI to PO are to be equally or near-equally balanced. However, equal-balancing of path-delays is hard to be realized even with help of extensive tuning due to various fabrication and runtime variations such as power consumption, thermal distribution and design errors to mention a few. In addition, clock skews due to the variations in the rise/fall time, and setup and hold time of the storage elements, clock frequency is limited within an increase only by a factor of 2 to 3 even by using the best available design method [5].

Wave pipeline is developed in both synchronous and asynchronous ways. Synchronous wave pipeline uses clock signal to control the synchronous movement of the data bits. It has been successfully implemented as modules in several commercial processors such as floating point unit in IBM 360/91 and external caches in HP PA8000. Asynchronous wave pipeline (clockless wave pipeline(CWP) is used interchangeably in this paper) uses request and acknowledgement signals, or only request signal instead of clock to serve as the reference. CWP is relatively more difficult to deploy than synchronous wave pipeline due to its explorativeness and a few technological hurdles as mentioned before. Clockless wave pipelined circuit has only been experimented in non-commercial sectors such as the two-phase CWP with request signal only as reported in [6] and [10]. The specific architectural model investigated in this paper is the two-phase clockless asynchronous wave pipeline [10] which is ideally supposed to yield the theoretical maximum of performance.
嗯,和buffered synchronous、buffered asynchronous和unbuffered synchronous外,又要多畫一張圖解了。可是我畫的出來嗎...

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